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- W2368166917 abstract "This paper presents a 30uw ultra-low power 10 bit successive approximation register(SAR) ADC which is realized in a 0.18um CMOS process.The design uses a fully-differential mode which is under 1.2V source supply,and 1V is used as reference voltage,the SNR of pre-simulation is 55.8dB.The two fully-symmetry capacitor-arraies are combined to the auto-zeroed comparator which is combined to the register.To improve the resolution,matching case,and reduce the whole capacitor area,one kind of new capacitor-array which is different from the classical ones is used,and all of the unit capacitors use the same size and shape.The design was implemented in Chartered 0.18um technology,and the test of the chip was fulfilled." @default.
- W2368166917 created "2016-06-24" @default.
- W2368166917 creator A5016932606 @default.
- W2368166917 date "2010-01-01" @default.
- W2368166917 modified "2023-09-26" @default.
- W2368166917 title "An Ultra-low power 10-bit SAR ADC" @default.
- W2368166917 hasPublicationYear "2010" @default.
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