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- W2368519862 abstract "An improved architecture for H.264 full-pel motion estimation using variable block size full-search block-matching algorithm is proposed in this paper.To obtain the highest data reuse efficiency and minimum I/O pin count while achieving 100% hardware efficiency,a systolic array and full pipeline architecture is adopted.The motion estimation processor is implemented using HJTC's 0.18 μm 1-poly 6-metal CMOS technology,which occupies a silicon area of 4 mm × 4 mm and operates at 125 MHz.Experimental results show that this circuit is capable of processing Supper HDTV video sequences(1920×1080,60 f/s) in real-time,and so it is applicable for H.264." @default.
- W2368519862 created "2016-06-24" @default.
- W2368519862 creator A5015984049 @default.
- W2368519862 date "2007-01-01" @default.
- W2368519862 modified "2023-09-25" @default.
- W2368519862 title "VLSI Design of High Performance Full-Search Block-Matching Full-Pel Motion Estimation Processor for H.264" @default.
- W2368519862 hasPublicationYear "2007" @default.
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