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- W2370180247 abstract "A low power methodology for fixed-point decimal multiplier in IC design was presented to optimize the number and width of the adders that were inside of synthesized multiplier. In terms of methodology implementation, it resolved the problem of optimization logic joining into optimized system, which existed in present low power design. The theoretical basis and the design method were explained. In order to get more objective and statistical test result, the methodology and implementation were used to optimize a radio-frequency module. FPGA test results show that logic utilization is reduced by 39.3%, the total number of registers used is reduced by 45.0%, and the total block memory bits utilization is reduced by 36.9%. These results show that the proposed low-power design is an effective method, which has good performance on optimizing the system including large-scale decimal multipliers, such as DSP and digital filter." @default.
- W2370180247 created "2016-06-24" @default.
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- W2370180247 date "2014-01-01" @default.
- W2370180247 modified "2023-09-26" @default.
- W2370180247 title "Low power methodology and implementation for fixed-point decimal multiplier" @default.
- W2370180247 hasPublicationYear "2014" @default.
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