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- W2370376792 abstract "This paper presented a simulation based functional verification methodology to validate a 32 bit RISC microprocessor (named as FDU32 below). In the scheme, pseudo random generation and pipeline focus generation are used as the main method to generate testbenches, and based on this the whole verification environment is set up to improve the automation and efficiency of the process. In addition, in order to guarantee the quality of the verification, code coverage analysis is used to evaluate and direct the effort of the verification. By the FPGA verification result and FDU32 chip functional testing result, the validity and the completeness of the functional verification methodology is proven." @default.
- W2370376792 created "2016-06-24" @default.
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- W2370376792 date "2004-01-01" @default.
- W2370376792 modified "2023-09-25" @default.
- W2370376792 title "Simulation-based Functional Verification Methodology of a 32-bit RISC Microprocessor" @default.
- W2370376792 hasPublicationYear "2004" @default.
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