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- W2370915146 abstract "A 4-bit 5 GS/s flash analog-to-digital converter(ADC) was designed and simulated in a 0.18 μm CMOS technology.Pipelining and low-swing operation both in analog and digital circuitry results in high-speed and low power.And the use of inductor in each comparator extends sampling rate without increasing power consumption.The ADC dissipates 65 mW of power from a 1.8 V supply while operating at 5 GHz.All signals in the ADC are differential,which ensures the immunity of the system to common mode noise,and the low-swing clock improves signal-to-noise ratio.The encoder converts thermometer code to an intermediate Gray code and then to a binary code.The intermediate Gray code is intended to reduce metastablity.Simulation results showed that the proposed ADC had an INL of 0.255 LSB and a DNL of 0.171 LSB,respectively,and the ENOB was up to 3.74 bits at 5 GS/s sampling rate for an input signal of 102.539 MHz." @default.
- W2370915146 created "2016-06-24" @default.
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- W2370915146 date "2009-01-01" @default.
- W2370915146 modified "2023-09-28" @default.
- W2370915146 title "A 4-Bit 5 GS/s Flash A/D Converter in 0.18 μm CMOS Technology" @default.
- W2370915146 hasPublicationYear "2009" @default.
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