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• W2371118666 abstract "The test of Integrated Circuits(IC) always encounter a lot of problems,like processing the huge test data volume,spending a long time to test and construct the complex test structure.This paper proposes a hybrid test method to compress test data volume based on multiple scan chains.Using pseudo-random pattern generator generates test vector which includes more does not care bits.The rest of vectors are stored by Automatic Test Equipment(ATE) directly.Both theory and experiment show that the proposed method can achieve better compression performance compared with the scan disabling-based BIST-aided Scan Test(BAST) scheme." @default.
• W2371118666 created "2016-06-24" @default.
• W2371118666 creator A5022985581 @default.
• W2371118666 date "2012-01-01" @default.
• W2371118666 modified "2023-09-24" @default.
• W2371118666 title "A Hybrid Test Data Compression Method of Multiple Scan Chains" @default.
• W2371118666 hasPublicationYear "2012" @default.
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