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- W2373850899 abstract "Famous IC vendors including Intel,AMD,IBM have scaled their IC technologies into 65nm.High-end IC design aiming at high performance has faced many challenges from cost,com- plexities of design and test,and etc.This paper describes two important and detail challenges: High power consumption and rampant process variations(PV)in nanometer regime.This paper includes following three parts.First,it consecutively describes components of IC power con- sumption,several negative influences originated from high power,and mainstream low-power de- sign methods.Second,it consecutively describes components of process variations,their negative influences on IC design,and statistical algorithm that studies about static delay analysis(STA), power analysis,and low-power design.Last,combining with the authors' own research,this pa- per simply presents hot research topics on these two challenges of next-generation IC design." @default.
- W2373850899 created "2016-06-24" @default.
- W2373850899 creator A5012423623 @default.
- W2373850899 date "2007-01-01" @default.
- W2373850899 modified "2023-09-28" @default.
- W2373850899 title "Power Consumption and Process Variations:Two Challenges to Design of Next-generation ICs" @default.
- W2373850899 hasPublicationYear "2007" @default.
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