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• W2375505746 abstract "Difficulties in further miniaturization of CMOS devices inspire new technologies that realize high performance and functionality in the devices without the scaling. In particular, new structures and materials alternative to bulk-Si substrates are now proposed to be applied to the channel layer in CMOS fabricated on a Si platform. Germanium on insulator (GOI) substrates attract much attention because of higher electronand holemobilities in Ge than those in Si. A wafer bonding technique using both Si wafers covered with SiO2 layers and Ge wafers with high crystallinity is advantageous to fabricate GOI and so-called engineered substrates with high-quality channel layers in a wafer scale. The process seems to be mature in the production of commercial silicon-on-insulator (SOI) substrates. However, in the case of GOI, one should pay attention to the bonded interface, i.e., the interface between the body of Ge channel layers and the buried oxide (BOX), which is to be of device grade quality. In this study, we perform prototypical wafer bonding to fabricate GOI substrates and characterize atomic structures, chemistry, and electrical properties of the Ge/BOX interface. GOI substrates were fabricated by wafer bonding of Ge(001) or Ge(111) wafers and p-type or n-type Si(001) wafers that have thermally-oxidized SiO2 layers. After the surfaces of Ge and SiO2 were contacted each other in a clean room at room temperature, the contacted wafers were annealed typically for 1 h at 300°C in a N2 atmosphere. Some of bonded wafers were post-annealed under various conditions. Detailed procedure is reported elsewhere [1-3] Atomic structures at the Ge(001)/BOX interface have been analyzed by cross-sectional high resolution transmission electron microscopy (TEM) [1]. Nanometersized hemi-spherical amorphous hollows were observed at the interfaces in the sample annealed at around 500oC in vacuum. The density of the hollows was observed to decrease with increase in the annealing temperature and atomically flat interfaces were obtained after the annealing at 800oC. Scanning TEM-electron energy loss spectroscopy (EELS) analysis using a fine electron probe was also performed to examine chemical species of the hollows. EELS spectra around an energy-loss region of Ge-L2,3, Si-L2,3 and Si-L1 edges were acquired across the hollows and flat Ge(001)/BOX interface. As a result, the hollows were identified to be Si-rich Si1-xGexO2 although it was difficult to estimate x value within the experiment. The mechanism of formation and disappearance of the hollows can be explained by two kinds of diffusion events of oxygen species: lateral diffusion along the Ge/BOX interface and vertical diffusion toward the surfaces of Ge layers. Since native oxide layers of GeOx should exist at the Ge/BOX interface and decompose at 420oC [4], movable oxygen species generate at the interfaces during the annealing. Although both diffusion events occur simultaneously, lateral diffusion and agglomeration of oxygen species along the interface is dominant at around 500oC, resulting in the formation of the Si-rich Si1-xGexO2 hollows. The reduction of the hollow density at high temperature (>500oC) possibly means that decomposition of the hollows preferentially occurs, in which most of oxygen species diffuse to the outside of Ge layer without forming the hollows. The electrical characterization of the Ge(001)/BOX interface has been performed by the four probe pseudo-MOSFET method [2] where the gate voltage VG was applied to the back Si side through an Al back gate electrode. We have confirmed transistor operation for all the fabricated samples and observed both hysteresis and threshold voltage shifts in measured channel conductance G versus VG curves. The hysteresis was remarkable in the sample annealed at lower temperatures less than 550oC but greatly decreased due to higher temperature annealing more than or equal to 550oC. Temperature dependence was also seen in the conduction type; n-type conduction was observed in the sample annealed at the lower temperatures and p-type at the higher temperature. This type change is possibly due to the presence of defect states with positive fixed charges near the Ge/BOX interface and the reduction by the high temperature annealing. Furthermore, we found that postannealing in the atmosphere including O2 gas with moderate concentration is effective in reducing the threshold voltage shift. The carrier mobility in the channel formed at the Ge/BOX interface can also be obtained from the G-VG curves. Derived electron mobility was found to change drastically with the annealing temperature and in the range of 500-800 cm/Vs in Ge(001)-OI substrates. On the other hand, we acquired a hole mobility of 320 cm/Vs in the p-channel inversion layer and an electron mobility of 1020 cm/Vs in the n-channel accumulation mode in Ge(111)-OI substrates [3]. These are high values, comparable to the electron mobility of Ge (111) MOSFET (~1100 cm/Vs) [5] and hole mobility of Ge(110)-OI formed by Ge condensation (~300 cm/Vs) [6]. Formation and characterization of GOI substrates were performed for realizing high mobility hetero channels in CMOS on a Si platform. We clarified that fabrication processes including wafer bonding and post-annealing strongly influence atomic structures, chemistry, and electrical properties at the Ge/BOX interface. Structural and electrical modification of related defects and interfacial states is a key to tailoring GOI substrates as a mobility enhancement solution in next generation CMOS." @default.
• W2375505746 created "2016-06-24" @default.
• W2375505746 date "2012-01-01" @default.
• W2375505746 modified "2023-09-24" @default.
• W2375505746 title "GOI substrates -Fabrication and Characterization-" @default.
• W2375505746 doi "https://doi.org/10.1149/ma2012-02/43/3191" @default.
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