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- W2375582230 abstract "A dynamic reconfiguration technique based on the partitioning of computing resources on many-core processor was introduced.According to the locality principle,both the hardware support,including dynamically reconfigurable sub-netting in NoC and dynamically reconfigurable Cache coherence protocol,and the scheduling algorithm for on-chip computing resources are designed to improve the utilization of the many-core processor.This paper also introduced the simulation platform for dynamically reconfigurable many-core processor,which is developed based on system level simulator Gem 5.The Cache coherence protocol with sub-netting and scheduling algorithm mentioned above was implemented.The simulation result proves the improvement for performance of the many-core processor." @default.
- W2375582230 created "2016-06-24" @default.
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- W2375582230 date "2013-01-01" @default.
- W2375582230 modified "2023-09-27" @default.
- W2375582230 title "Design of System Level Simulation Platform for Dynamic Reconfigurable Many-Core Processor" @default.
- W2375582230 hasPublicationYear "2013" @default.
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