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• W23758320 abstract "The logic capacity of reconfigurable devices has been increased drastically in the past ten years. However, the design productivity is increasing at a lower pace. It is desirable to have a higher level of abstraction to bridge this design productivity gap. This will allow us to make the most of the abundant logic resources on our devices with a shorter design time and at a lower labor cost. This work has built a compiler that takes C code as input and generates synthesizable VHDL code targeting reconfigurable devices. This document first introduces our execution model. The compiler builds this model in VHDL. At the heart of each compiler or synthesis tool is an intermediate representation around which the tool is built. The intermediate representation of our compiler supports concurrency, both explicitly and implicitly, as well as the instantiation of and accesses to on-chip storage structures. It records information about loop types, memory interfacing, instruction predication and pipelining. Special instructions for efficient data-path generation are introduced. Memory bandwidth is one of the dominant factors that effect the computing performance on reconfigurable devices. We present our input data reuse approach that relieves the memory bandwidth pressure. The compiler generates a buffer, called smart buffer, in VHDL, to store and reuse the fetched data elements from the input data stream. The smart buffer initiatively pushes the stored data into the data-path. The compiler produces each smart buffer based on the input C loop. Therefore the size and behavior of a smart buffer is tailored specifically for the corresponding loop. The compiler exploits both the loop-level and the instruction-level parallelism when generating data-path. The generated data-path can execute one loop iteration per clock-cycle when there is no loop-carried dependency. Predication is used to schedule the action of data-path and to handshake with buffers. Our compiler supports the use of pre-designed intellectual property (IP) cores as a function call in the C input code. IP cores vary drastically with respect to their control and timing protocol. The compiler wraps IP cores so they can be controlled by the same predication mechanism as the reminder of the data-path. To do so, users provide the high-level description of a wrapper, which is based on C with timing information, and then the compiler automatically generates the synthesizable wrapper in VHDL code. This IP wrapping mechanism can be used to load/unload multiple IP cores at run-time with the dynamic partial reconfiguration technique." @default.
• W23758320 created "2016-06-24" @default.
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• W23758320 date "2006-01-01" @default.
• W23758320 modified "2023-09-27" @default.
• W23758320 title "Automatic generation of vhdl from c for code acceleration on reconfigurable devices" @default.
• W23758320 hasPublicationYear "2006" @default.
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