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- W2375868909 abstract "In order to increase the speed of RS(Reed-Solomon) decoder and reduce the cost,the Verilog HDL(Hardware Description Language) design method of the RS decoder based on FPGA(Filed Programming Gate Array) is illustrated.In this paper,the basic principle of RS codes is introduced.According to RS decoding principle in Temporal of RS decoder,it converts syndrome computation,Chien search,BM(Berlekamp-Massey) iterative algorithm,Forney computation to Verilog HDL,which are suitable to simulate on computer.Using Quartus of Altera,it has compiled computation module above generated Circuits of themselves,and simulated.It finally demonstrates the hardware performance of RS(239,255) decoder based on the FPGA of ACEX1K which works at 14 MHz clock at most." @default.
- W2375868909 created "2016-06-24" @default.
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- W2375868909 date "2006-01-01" @default.
- W2375868909 modified "2023-09-23" @default.
- W2375868909 title "Realization of RS(239,255) Decoder Based on FPGA" @default.
- W2375868909 hasPublicationYear "2006" @default.
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