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- W2376882076 abstract "3-D technology that uses Through Silicon Via(TSV)providing communication links for dies in vertical direction provides many benefits including high density, low power, and small form-factor. It has drawn public attention at the industry and academia. With the number of stacked dies increasing, a failed TSV may increase the cost and decrease the yield severely. A TSV fault-tolerant architecture is proposed in the paper. The chip is divided into several density region first, then the repair TSVs are allotted according the density region's density, the larger the density, the more repair TSVs are allotted, which not only reduce the number of repair TSVs, the density of the all TST could be redistribution. The hardware and the repair rate are also analyzed in the paper, which show the proposed scheme could recover most of the failed chips with reasonable cost. The experimental results also prove the efficiency of the proposed scheme." @default.
- W2376882076 created "2016-06-24" @default.
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- W2376882076 date "2015-01-01" @default.
- W2376882076 modified "2023-09-25" @default.
- W2376882076 title "Fault-tolerant design for TSVs of 3D stacked ICs" @default.
- W2376882076 hasPublicationYear "2015" @default.
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