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- W2377837249 abstract "In the latest video compression standard,a new 8-tap Motion Estimation( ME) interpolation filtering is adopted in High Efficiency Video Coding( HEVC). Although the new 8-tap filter can improve the precision compared w ith the 6-tap interpolation filter used in H. 264 / AVC,it also increases the Very Large Scale Integration( VLSI) efficient area. A high performance VLSI architecture for HEVC interpolation filter is proposed. A fast and hardw areimplementation-friendly interpolation filtering algorithm is presented. Based on the fast algorithm,this paper designs and realizes the interpolation filter VLSI structure of the reconfigurable and the multiplexing of the cell block to reduce the efficient area of hardw are. Experimental results show that,compared w ith the non-optimized VLSI architecture,the proposed VLSI architecture not only reduces the area and improves the w orking frequency,but also saves a lot of RAM.It can support the real-time processing of 4: 2: 0 format 3 840 × 2 160 video sequences." @default.
- W2377837249 created "2016-06-24" @default.
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- W2377837249 date "2015-01-01" @default.
- W2377837249 modified "2023-09-28" @default.
- W2377837249 title "An Efficient VLSI Architecture Design of High Efficiency Video Coding Interpolation Filtering" @default.
- W2377837249 hasPublicationYear "2015" @default.
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