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- W2378481471 abstract "in this paper ,based on the butlt-in self-test technique to logic circuil ,a nme approach is pro-posed to optimize input probability of digital circuit. After the worst faults are found and their circuitmodel are created the output signals of these models will be compressed by “1” counter. Fault detectprobabilities for the worst faults can be obtained by analyzing compact data. Finally, using the relationbetween the input probability and the fault detect probabilily ,we propose a new algorithm to optimzethe primary input probainlily of the circuit. So the shortest test length can he received." @default.
- W2378481471 created "2016-06-24" @default.
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- W2378481471 date "1994-01-01" @default.
- W2378481471 modified "2023-09-25" @default.
- W2378481471 title "On the Input Probability for Built-in Test" @default.
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