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- W2380482519 abstract "This paper designs a low power instruction Cache by adding a Line Buffer between CPU and instruction Cache to reduce the on-chip cache memory access activities,consequently it decreases the energy consumption of the Cache memory.What’s more,it also minimizes the Cache miss penalty by adding refill engine to the Line Buffer.Simulation results show that the design can not only reduce the power consumption but also improve the instruction Cache performance." @default.
- W2380482519 created "2016-06-24" @default.
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- W2380482519 date "2011-01-01" @default.
- W2380482519 modified "2023-09-23" @default.
- W2380482519 title "Low power instruction Cache design" @default.
- W2380482519 hasPublicationYear "2011" @default.
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