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- W2380523956 abstract "In the current ASIC functional verification flow, the debuggability for FPGA-prototype verification systems is a main obstacle that restricts the verification speed. A new simulated memory technology is provided in this paper. In this technology, memory accesses in the FPGA board are mapped to a PC and simulated by software.Functional verification engineers can record and analyze the executing track of test use cases,and set the breakpoints of the memory access transactional level conveniently, which greatly improves the debuggability of the verification board. Meanwhile, the complexity and cost of simulated memory are lower than actual hardware with a large memory system,which is helpful to decrease the complexity of the FPGA-prototype verification board." @default.
- W2380523956 created "2016-06-24" @default.
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- W2380523956 date "2007-01-01" @default.
- W2380523956 modified "2023-09-23" @default.
- W2380523956 title "A FPGA-Prototype Verification System Based on Simulated Memory" @default.
- W2380523956 hasPublicationYear "2007" @default.
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