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- W2381236594 abstract "A digital IF receiver and recovery system is proposed,which is divided into optical receiver unit,FPGA core unit and QDUC unit.The optical receiver unit completes high-speed serial data conversion using high-speed serializer / deserializer TLK1501.The FPGA core unit achieves a data decoding and CRC check.In addition,FPGA configures TLK1501 and AD9957.The QDUC unit achieves DUC and D/A conversion.Results of experiments verify that the system has the advantages of good real-time performance,low bit error rate,good stability and strong anti-jamming ability." @default.
- W2381236594 created "2016-06-24" @default.
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- W2381236594 date "2012-01-01" @default.
- W2381236594 modified "2023-09-25" @default.
- W2381236594 title "A Digital IF Receiver and Recovery System Based on FPGA" @default.
- W2381236594 hasPublicationYear "2012" @default.
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