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- W2381622032 abstract "Adder is the basic cell of arithmetic operation, many structures can be used to implement it, and the adder designed by different method consumes different number of resource and has a different speed respectively. This paper studies the structures and methods of adder based on the FPGA, analyses and compares the performance of each adders, moreover design a 8b adder based on the structure of pipeline. Carry out it by utilizing the Hard Describe Language (VHDL and Verilog HDL) and ISE software package V5.2i from Xilinx and simulating it by Modelsim software, and evaluation and comparison the performance (area and speed) of it. The result of experiment indicates that the pipeline adder is faster others." @default.
- W2381622032 created "2016-06-24" @default.
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- W2381622032 date "2005-01-01" @default.
- W2381622032 modified "2023-09-25" @default.
- W2381622032 title "Design and Implementation of High-speed Adder Based on FPGA" @default.
- W2381622032 hasPublicationYear "2005" @default.
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