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- W2381858791 abstract "A two-stage clock disabling architecture was developed to reduce average and peak power level during digital circuit testing.The circuit under test(CUT) is partitioned according to the test stimulus compression condition and the test response compression condition with only sub-circuits activated in each clock cycle to reduce peak power.The experimental results show that the total power is reduced to 0.74% that of the traditional full scan scheme,peak power is reduced to 18.41%,peak power in the capture stage is reduced to 11.32%.Hereby,the test power and other factors related to the test application cost are greatly reduced compared with the traditional full scan scheme." @default.
- W2381858791 created "2016-06-24" @default.
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- W2381858791 date "2007-01-01" @default.
- W2381858791 modified "2023-09-27" @default.
- W2381858791 title "Clock-disabling scheme to reduce test power" @default.
- W2381858791 hasPublicationYear "2007" @default.
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