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- W2384392936 abstract "In the paper,we propose one design of a configurable MIMO detector based on FPGA,whose throughput reaches 100Mbit/s.This detector can switches between MMSE and QRM-MLD(Maximum Likelihood Detection with QR decomposition and M-algorithm) algorithms according to the channel status information from the channel estimation module.The design is based on the scene of 4 X 4 MIMO.The hardware resources are reused by the matrix's inversion of MMSE and the QR decomposition of QRM-MLD.By the implementation results on FPGA of Xilinx,this kind architecture design will save the FPGA multiplier and logic resources greatly than two separate detectors." @default.
- W2384392936 created "2016-06-24" @default.
- W2384392936 creator A5064295553 @default.
- W2384392936 date "2009-01-01" @default.
- W2384392936 modified "2023-09-23" @default.
- W2384392936 title "Design of a Configurable MIMO Detector Based on the FPGA" @default.
- W2384392936 hasPublicationYear "2009" @default.
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