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- W2384713940 abstract "The present paper proposes a high-speed FPGA architecture of discrete wavelet transform (DWT) as well as inverse DWT (IDWT), and using Daubechies 8 wavelet implements the system.And it is verified on the DE2 development board, after optimized, the maximum clock frequency of DWT and IDWT can respectively achieve 217.72 MHz and 217.58 MHz.Compared with similar work in other literatures, the design has an obvious advantage of the maximum processing speed. On this basis, considering the request of versatility, a universal FPGA architecture is also designed in this paper. And the proposed architecture is characteristic of versatility and can efficiently implement varieties of DWT and IDWT. In design scheme, DA (Distributed Arithmetic),LUT (Look-Up Table) architecture and pipeline technology are used to optimize the design." @default.
- W2384713940 created "2016-06-24" @default.
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- W2384713940 date "2009-01-01" @default.
- W2384713940 modified "2023-09-25" @default.
- W2384713940 title "Design of high-performance discrete wavelet transform based on FPGA" @default.
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