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- W2385803157 abstract "A full search block matching algorithm of a systolic architecture was implemented in RTL level VHDL for low bit rate video compression applications.This implementation was synthesized for Xilinx FPGA family,Vitex2-Pro.The results of area occupation and maximum operating frequency are presented.This architecture is able to be applied in a real-time low bit rate application.Furthermore,there are three parameters in the implementation controlling the range of search area." @default.
- W2385803157 created "2016-06-24" @default.
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- W2385803157 date "2006-01-01" @default.
- W2385803157 modified "2023-09-23" @default.
- W2385803157 title "Implementation of a full search block matching algorithm using FPGA" @default.
- W2385803157 hasPublicationYear "2006" @default.
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