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- W2386755621 abstract "This paper provides the design of multiple re-trigger memory test system based on CPLD,and introduces the system hardware design and the CPLD control principle.The CPLD control circuit is performed the wave simulation.This system features smaller size and lower power consumption,and it is able to repeatedly measure re-trigger signals in realtime.The record of each signal has a negative delay.Without adjusting procedures,the system design accurately records complex waveform.This design has important significance to the application of re-trigger technology in memory test system." @default.
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- W2386755621 date "2009-01-01" @default.
- W2386755621 modified "2023-09-23" @default.
- W2386755621 title "Design of multiple re-trigger memory test system based on CPLD" @default.
- W2386755621 hasPublicationYear "2009" @default.
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