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- W2387265890 abstract "Based on the idea of mapping the loops onto the reconfigurable array can improve the performance, the paper proposes a heuristic hardware-software partition algorithm which partitions the big loop into two parts:one is in the processor and another in the array.The objective of the algorithm is to minimize the communication of the two parts.The partition algorithm reduces 13%～29% of execution time compared with original techniques..The technology has been verified on the platform of FPGA with some kernel algorithms of multimedia applications, such Motion Estimation of H.264, and IDCT of MPEG-2.With the same scale of reconfigurable array, the performance is 3.5 times higher than the similar researches." @default.
- W2387265890 created "2016-06-24" @default.
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- W2387265890 date "2009-01-01" @default.
- W2387265890 modified "2023-09-24" @default.
- W2387265890 title "Hardware-Software Partition Technology of Loops for Reconfigurable Processor" @default.
- W2387265890 hasPublicationYear "2009" @default.
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