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- W2387514935 abstract "A phase locked loop (PLL) frequency synthesizer with an input clock of 32 768 Hz is designed, which can generate 5 frequencies with 1 250, 1 500, 2 000, 2 500, and 3 000 as multiplying factors. The design is based on 1st Silicon 2.5 V 0.25 μm technology. Simulations using Cadence Artist Analog show that the circuit has a short lockup time with little jitter. Theory on the parameter design of the PLL frequency synthesizer is studied and summarized, and structures of the sub-circuits are optimized. And finally, layout design based on the requirements of MPW is described." @default.
- W2387514935 created "2016-06-24" @default.
- W2387514935 creator A5059066363 @default.
- W2387514935 date "2005-01-01" @default.
- W2387514935 modified "2023-09-25" @default.
- W2387514935 title "A PLL Frequency Synthesizer with High Multiple-Frequency" @default.
- W2387514935 hasPublicationYear "2005" @default.
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