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- W2387668857 abstract "This paper discusses the sign prediction and iterative calculation of the CORDIC algorithm in the rotation mode,and uses a parallel computation technique to accelerate it.We propose the sign prediction mechanism of subsection sign prediction and adding the correcting rotation,and use a method of unfolded subsection iteration and a three-in adder tree to perform the iterative calculation of the CORDIC algorithm.These techniques effectively reduce the correcting rotations and the cost of hardware,and enhance the computing performance.Finally the parallel CORDIC architecture is implemented on the FPGA chip of StratixII from Altera." @default.
- W2387668857 created "2016-06-24" @default.
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- W2387668857 date "2008-01-01" @default.
- W2387668857 modified "2023-09-23" @default.
- W2387668857 title "Research of the Parallel CORDIC Algorithm and Its Implementation in FPGA" @default.
- W2387668857 hasPublicationYear "2008" @default.
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