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- W2388320073 abstract "Aiming at the request of low power and small area of UHF RFID tags,this paper presents a baseband processor, which is compatible with theEPCTM Class-1 Generation-2 UHF RFID Protocol.The method of module division and a new architecture are proposed based on the analysis of the tag's function.The lowest frequency that a tag needs is discussed and computed.A power management module is designed for both power reduction and scheduling modules in order to make them work in a correct way.The pipelining way of encoding the outputs is adopted.This paper also designs a simplified memory interface.The result of simulation accords with the protocol,and the design has been synthesized, whose area is about 7 200 gates.The circuit can be applied to a UHF RFID tag." @default.
- W2388320073 created "2016-06-24" @default.
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- W2388320073 date "2010-01-01" @default.
- W2388320073 modified "2023-09-22" @default.
- W2388320073 title "Design of a Digital Baseband Processor for UHF RFID Tags" @default.
- W2388320073 hasPublicationYear "2010" @default.
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