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- W2390997091 abstract "The hardware implementation of satellite image divided block decoding system design isdiscussed. A method for image divided block decoding is proposed,which uses the pipeline and multi-channel parallel operation to carry out high-speed decoding of the image stream and the IP Core of FPGA to achieve chip memory.So it can reduce the design complexity and external RAM.By the features of asynchronous FIFO it can read and write,and achieve detection and stream decoding simultaneously.The modeling and realization are implementation by VHDL. The experimental results show that this scheme,with less hardware resources,could realize fast decoding,and achieve real-time image-stream decoding and accuracy.And with its portability,it can be applied to many areas of image processing." @default.
- W2390997091 created "2016-06-24" @default.
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- W2390997091 date "2011-01-01" @default.
- W2390997091 modified "2023-09-23" @default.
- W2390997091 title "FPGA-based Design of Image Block Decoding System" @default.
- W2390997091 hasPublicationYear "2011" @default.
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