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- W2392485307 abstract "Logic soft errors are radiation induced transient errors in sequential elements(flip-flops and latches) and combinational logic part.The faults tolerant architecture mentioned in this paper combines latch-based design and time redundancy techniques to achieve high fault tolerant efficiency at low area and speed penalty.ISCAS′89 benchmark circuits were used as test vehicle to validate the approach.The obtained experiment results show that high fault tolerant efficiency can be achieved by means of meaningful hardware and performance cost." @default.
- W2392485307 created "2016-06-24" @default.
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- W2392485307 date "2009-01-01" @default.
- W2392485307 modified "2023-09-23" @default.
- W2392485307 title "Research and Implementation on an Efficient Logic Soft Errors Tolerant Architecture" @default.
- W2392485307 hasPublicationYear "2009" @default.
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