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- W2392517299 abstract "A design of quadric group demultiplexer for PDH(plesiochronous digital hierarchy) communication is discussed based on 10k30 FPGA(Field Programmable Gate Array).The frame synchronization of the quadric group signal at the speed of 8 448 Kbit/s is detected and the quadric group signal is divided into four signals in FPGA by the VHDL(Very High Speed Intergrated Circuit Hardware Description Language) program.In addition,the plan of hardware and some of the VHDL codes and waveforms of simulation are also listed." @default.
- W2392517299 created "2016-06-24" @default.
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- W2392517299 date "2006-01-01" @default.
- W2392517299 modified "2023-09-24" @default.
- W2392517299 title "Design of Quadric Group Demultiplexer for PDH Communication Based on FPGA" @default.
- W2392517299 hasPublicationYear "2006" @default.
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