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- W2392676970 abstract "As layered-decoding algorithm can not be used by non-layered LDPC codes,a new architecture for layered-decoding algorithm is proposed in this paper.Different from traditional architecture,the new design uses parallel updating among layers and serial updating within each layer.With the same variable nod updated at different time in different layers,message for every variable can be updated layer by layer.The design can complete decoding for 3/4 code rate,8 192 code length,(3,12)regular non-layered QC-LDPC codes.The whole design is synthesized under Cyclone Ⅲ EP3C120 FPGA of Altera,Inc.After routed,the highest clock frequency can reach 45.44 MHz.When the maximum iteration number is set to 5,the decoder throughput can reach 47.6 Mbps." @default.
- W2392676970 created "2016-06-24" @default.
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- W2392676970 date "2012-01-01" @default.
- W2392676970 modified "2023-09-26" @default.
- W2392676970 title "Layered Decoder Design for Non-layered LDPC Codes Based on FPGA" @default.
- W2392676970 hasPublicationYear "2012" @default.
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