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- W2393215252 abstract "With the development of digital satellite navigation receiver technology,the digital integrated circuits of receiver are becoming larger and larger.Simulation capabilities have become a bottleneck of restricting manufacturing capabilities for more complex,more large-scale digital receiver integrated circuit(IC).The traditional simulation software NC-Sim can get more visible waveforms while the simulation speed is very slow.Another traditional one,field programmable gate array(FPGA)online simulation by loading Chip-Scope gets faster simulation speed but has less visible waveform,it gets limited data length storage,and is unable to set trigger conditions and takes a lot of time to re-synthesis,layout after each change.It is unable to adapt to the demand of modern digital satellite navigation receiver IC development.For meeting demand of developing BeiDou navigation satellite system(BDS)receiver baseband processing IC,in this paper a satellite navigation receivers' universal verification platform is designed based on palladium hardware simulation accelerator,which can receive baseband analog data in real-time and fully simulate actual working conditions of satellite navigation receivers.Compared with traditional methods,this technology contains the following outstanding performance for large-scale IC design:shortest synthesis time,least simulation time,all signals' waveform is visible,data storage length is greater and the trigger conditions can be flexibly configured." @default.
- W2393215252 created "2016-06-24" @default.
- W2393215252 creator A5043028039 @default.
- W2393215252 date "2014-01-01" @default.
- W2393215252 modified "2023-09-23" @default.
- W2393215252 title "Design of Satellite Navigation Receivers' Universal Verification Platform Based on Palladium Accelerator" @default.
- W2393215252 hasPublicationYear "2014" @default.
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