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- W2396411503 abstract "This paper describes the design of low power 12bit Digital-to-Analog Converter(D/A Converter) using Pseudo-Segmentation method which shows the conversion rate of 80MHz and the power supply of 1.8V with 0.18um CMOS n-well 1-poly 6-metal process for advanced wireless communication system. Pseudo-segmentation method used in binary decoder consists of simple parallel buffer is employed for low power because of simpler configuration than that of thermometer decoder. Also, using deglitch circuit and swing reduced drivel reduces a switching noise. The measurement results of the proposed low power 12bit 80MHz CMOS D/A Converter shows SFDR is 66.01dBc at sampling frequency 80MHz, input frequency 1MHz and ENOB is 10.67bit. Integral nonlinearity(INL) / Differential nonlinearity(DNL) have been measured . Glich energy is measured . Power dissipation is 46.8mW at 80MHz(Maximum sampling frequency) at a 1.8V power supply." @default.
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- W2396411503 date "2008-01-01" @default.
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- W2396411503 title "Design of Low Power 12Bit 80MHz CMOS D/A Converter using Pseudo-Segmentation Method" @default.
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