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- W2398366931 abstract "Energy consumption in the instruction cacheaccounts for a significant portion of the total processor energy consumption. Therefore, reducing energy consumption in the instruction cache is important in designing embedded processors. This paper proposes a method for reducing dynamic energy consumption in the instruction cache by partitioning it to smaller (less energy-consuming) sub-caches. When a request comes into the proposed cache, only one sub-cache is accessed by utilizing the locality of applications. By contrast, the other sub-caches are not accessed, leading todynamic energy reduction. In addition, the proposed cache reduces dynamic energy consumption by eliminating the energy consumed in tag matching. We evaluated the energy efficiency by running cycle accurate simulator, SimpleScalar. with power parameters obtained from CACTI. Simulation results show that the proposed cache reduces dynamic energy consumption by compared to the traditional direct-mapped instruction cache." @default.
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- W2398366931 date "2007-01-01" @default.
- W2398366931 modified "2023-09-23" @default.
- W2398366931 title "Energy-aware Instruction Cache Design using Partitioning" @default.
- W2398366931 hasPublicationYear "2007" @default.
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