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- W2399565531 abstract "The arrangement graph, which is a viable interconnection scheme for parallel and distributed systems, has been proposed as an attactive altemative to the n-cube. However, A fault tolerant design model which is well suitable for the arrangement graph doesn't has been proposd until recently, but fault tolerant design modelsfor many schemes have been proposed ina large number of paper. So, our paper presents a new fault tolerant design technique suited for the arrangement graph. To maintains the previous structures when it ocurs a fault in the current processing, the scheme properly sugbstitutes a fault-componnent into the existing structures by adding a spare component. the first of all, it converts arrangement graph into a circulant graph using the hamiltonian property and then uses automorphism of circulant graph to tolerate faults. Also, We optimize the cost of rate fault tolerant architectures by adding exactly k spare processor while tolerating up to k processor and minimizing the maximum number of limks per processor. Specially, we proposes a new techniue to minimize the maximum number of links." @default.
- W2399565531 created "2016-06-24" @default.
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- W2399565531 date "1998-01-01" @default.
- W2399565531 modified "2023-09-23" @default.
- W2399565531 title "Minimum Design of Fault-Tolerant Arrangement Graph for Distributed &Parallel System" @default.
- W2399565531 hasPublicationYear "1998" @default.
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