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• W2400672607 abstract "This paper presents a new bit-parallel multiplier for the finite field GF (2) generated with an irreducible all-one polynomial. Redundant representation is used to reduce the time delay of the proposed multiplier, while a three-term Karatsuba-like formula is combined with this representation to decrease the space complexity. As a result, the proposed multiplier requires about 10 percent fewer AND/XOR gates than the most efficient bit-parallel multipliers using an all-one polynomial, while it has almost the same time delay as the previously proposed ones." @default.
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• W2400672607 date "2012-01-01" @default.
• W2400672607 modified "2023-09-24" @default.
• W2400672607 title "Low complexity bit-parallel GF(2 m ) multiplier for all-one polynomials." @default.
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