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- W2401743419 abstract "We proposed an unified design methodology and verification platform for giga-scale System on Chip (SoC). According to the growth of VLSI integration, the existing RTL design methodology has a limitation of a production gap because a design complexity increases. A verification methodology need an evolution to overcome a verification gap. The proposed platform includes a high level synthesis, and we develop a power-aware verification platform for low power design and verification automation using it's results. We developed a verification automation and power-aware verification methodology based on control and data flow graph (CDFG) and an abstract level language and RTL. The verification platform includes self-checking and the coverage driven verification methodology. Especially, the number of the random vector decreases minimum 5.75 times with the constrained random vector algorithm which is developed for the power-aware verification. This platform can verify a low power design with a general logic simulator using a power and power cell modeling method. This unified design and verification platform allow automatically to verify, design and synthesis the giga-scale design from the system level to RTL level in the whole design flow." @default.
- W2401743419 created "2016-06-24" @default.
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- W2401743419 date "2010-01-01" @default.
- W2401743419 modified "2023-09-27" @default.
- W2401743419 title "Unified Design Methodology and Verification Platform for Giga-scale System on Chip" @default.
- W2401743419 hasPublicationYear "2010" @default.
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