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• W2414581469 abstract "Digital integrated circuits have grown in size and density at an exponential rate since their inception. With this growth, the time and effort involved in verifying the design has also increased significantly. Verification by circuit simulation has become the only practical solution. Many verification solutions exist, but the performance of these solutions is not keeping up with the growth of the designs. In addition, the memory requirement of simulating large designs is also growing at an extremely fast rate. Three techniques for high speed digital circuit simulation are presented: unit-delay, multi-delay and packed vector simulation. All of the techniques presented are based on the Inversion algorithm. The Inversion algorithm is a novel technique for event-driven, zero-delay, gate level simulation. To perform timing analysis, a crucial part of the verification process, a simulator must be able to perform unit-delay and multi-delay simulation. The Inversion algorithm is able to perform very efficient zero-delay simulation by using statically linked data structures to represent the components of the circuit during simulation. For unit-delay and multi-delay simulation, circuit components may be simulated multiple times for each input vector. To retain the use of static data structures, multiple copies of each data structure must be available during circuit simulation. This dissertation presents several techniques to significantly reduce the number of data structures created for simulation by analyzing the circuit and creating the minimum number of data structures necessary to correctly simulate the circuit. Compiled code simulators have been performing parallel simulation on a uni-processor machine for many years. Packed vector simulation can be accomplished by packing the single bit value of a signal for each input vector to be simulated into a word. Because workstations can perform bit-wise logical operations, each of the bits in the word can represent the signal value for a specific input vector. The Inversion algorithm does not represent gate values as bits and does not perform logical operations for simulation. Instead the algorithm uses a counting technique to perform simulation and stores the state of a gate as a count. To perform parallel simulation on a uni-processor machine with the Inversion algorithm, the counts representing a gate's state must be packed together and manipulated in parallel. A technique is presented that allows the Inversion algorithm to perform parallel simulation with a significant increase in the performance of the simulator." @default.
• W2414581469 created "2016-06-24" @default.
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• W2414581469 date "2001-01-01" @default.
• W2414581469 modified "2023-09-26" @default.
• W2414581469 title "Techniques for high-speed digital circuit simulation" @default.
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