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- W2419280736 abstract "Through Silicon Vias (TSV) play an important role in 3D chip integration. Its features include: providing vertical interconnection, decreasing the area of routing, and increasing the bandwidth. Effective and efficient testing for correct operation of TSVs is an essential issue for 3D ICs. This work focuses on crosstalk faults with different impact ranges and proposes a TSV grouping method to test as many TSVs simultaneously as possible. Based on the results of the TSV grouping, we also implement a high-efficiency, low-area-overhead TSV test architecture." @default.
- W2419280736 created "2016-06-24" @default.
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- W2419280736 date "2016-04-01" @default.
- W2419280736 modified "2023-09-26" @default.
- W2419280736 title "3D-IC test architecture for TSVs with different impact ranges of crosstalk faults" @default.
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- W2419280736 doi "https://doi.org/10.1109/vlsi-dat.2016.7482554" @default.
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