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- W2433302557 abstract "Continuous scaling of CMOS technology makes it possible to integrate a large number of heterogeneous devices that need to communicate efficiently on a single chip. For this efficient routers are needed to takes place communication between these devices. This paper gives the design of on-chip routers based on optimizing power consumption and chip area. Proposed architecture of on-chip router in this paper give the results in which power consumption is reduced and silicon area is also minimize." @default.
- W2433302557 created "2016-06-24" @default.
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- W2433302557 date "2011-01-01" @default.
- W2433302557 modified "2023-09-24" @default.
- W2433302557 title "Design and Analysis of On-Chip Router for Network On Chip" @default.
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