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- W2434594172 abstract "In this work, design of Fractional-N Frequency Synthesizer using PLL has been investigated. The simulation is done in 0.18 μm CMOS technology with CADENCE tools using UMC foundry models. The different parts of synthesizer discussed in detail. Three different phase detector architectures are implemented. High speed TSPC DFF has designed to divide the frequency of GHz range. The prescalar is modified to have a delay of 80 ps only. For VCO, a multi layer inductor is used to save the area. The phase noise can be further reduced with a ΔΣ modulator in feedback loop. The designed frequency synthesizer targets RF applications like DVB-SH, WLAN, 802.11, bluetooth, cordless phones and remote control. Keyword: VCO, TSPC DFF, phase detector." @default.
- W2434594172 created "2016-06-24" @default.
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- W2434594172 date "2011-01-01" @default.
- W2434594172 modified "2023-09-27" @default.
- W2434594172 title "FRACTIONAL-N FREQUENCY SYNTHESIZER DESIGN FOR RFAPPLICATIONS" @default.
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