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• W24603911 abstract "Partitioning digital circuits has become a key problem in the Computer Aided Engineering area during the last years. Design benefits of new technologies like Multi-Chip-Module designs or logic emulation strongly depends on partitioning results. Most published approaches are based on abstract graph models constructed from flat net-lists, thus taking only connectivity information into consideration. The approach presented in this paper uses specific information about design modules, higher level design structures and hierarchy to create a cluster structure. Followed by a standard iterative improvement algorithm our results are comparable to best partitioning results published before and outperform them in special cases." @default.
• W24603911 created "2016-06-24" @default.
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• W24603911 date "1996-12-31" @default.
• W24603911 modified "2023-09-26" @default.
• W24603911 title "Circuit partitioning using high level design information" @default.
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• W24603911 hasPublicationYear "1996" @default.
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