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- W2464720912 abstract "A novel extension structure, which consists of a highly doped elevated layer and an underlying diffusion layer, is proposed in order to realize a shallow extension structure with a low sheet resistance. Using device simulation, we calculated cut-off characteristics, the drive current, the overlap capacitance and the propagation delay time of complementary metal oxide semiconductor (CMOS) inverter of 35 nm gate length devices with the elevated extensions. By considering the physical meaning of these results, we show the design guidelines for this structure for the minimization of tpd. Since there is a trade-off between an overlap capacitance and a drive current, there are minima of tpd in terms of the elevated extension thickness, the distance between a gate and the elevated extension and the gate sidewall thickness. With the optimal device parameters, the device with the elevated extensions has good cut-off characteristics and a high drive current. It was also revealed that tpd of the device with elevated extensions is smaller than that of the conventional device." @default.
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- W2464720912 date "2001-01-01" @default.
- W2464720912 modified "2023-09-24" @default.
- W2464720912 title "Elevated Extension Structure for 35 nm MOSFETs" @default.
- W2464720912 doi "https://doi.org/10.7567/ssdm.2001.f-2-3" @default.
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