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- W2470607215 abstract "With a growing number of cores integrated in a single chip, the efficiency of inter-core direct memory access (DMA) transfers has an increasingly significant impact on the overall performance of parallel applications running on network-on-chip (NoC) processors. In this paper we propose HyDMA, a low-latency inter-core DMA approach based on a hybrid packet-circuit switching NoC. With dynamic setup and lengthening of circuit channels composing of bidirectional links, HyDMA can achieve both high flexibility of packet switching and low communication latency of circuit switching for concurrent DMA transfers. Experimental results prove HyDMA exhibits high efficiency with marginal hardware overhead." @default.
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- W2470607215 date "2016-01-01" @default.
- W2470607215 modified "2023-10-18" @default.
- W2470607215 title "HyDMA: low-latency inter-core DMA based on a hybrid packet-circuit switching network-on-chip" @default.
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- W2470607215 doi "https://doi.org/10.1587/elex.13.20160529" @default.
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