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- W2479661333 abstract "This paper presents a second order multi-bit incremental analog-to-digital converter with two-phase feedback DAC control logic, insensitive to capacitor mismatches and with enhanced performance in multi-bit implementation. Besides, the proposed technique eliminates the complexity of dynamic element matching and relaxes the Op-amp's settling time. Behavioral simulations show that it can achieve 115.55 dB SNDR at 128 clock cycles using a 7-bit quantizer without dynamic element matching." @default.
- W2479661333 created "2016-08-23" @default.
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- W2479661333 date "2016-06-01" @default.
- W2479661333 modified "2023-10-16" @default.
- W2479661333 title "A high resolution multi-bit incremental converter insensitive to DAC mismatch error" @default.
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- W2479661333 doi "https://doi.org/10.1109/prime.2016.7519459" @default.
- W2479661333 hasPublicationYear "2016" @default.
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