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- W2479930167 abstract "This chapter describes the process of mapping the image compression algorithm SPIHT onto reconfigurable logic architecture. It provides a discussion of why adaptive logic is required, as opposed to an ASIC, along with background material on SPIHT and analyzes and evaluates several discrete wavelet transform hardware architectures. The chapter also presents two major modifications to the original image compression algorithm, which are required to build a reconfigurable hardware implementation that includes the storage elements necessary for each wavelet coefficient, and a modification to the original SPIHT algorithm created to parallelize the computation. It discusses the effects these modifications have on the final compression results and the trade-offs involved and describes how the updated SPIHT algorithm is mapped onto the Annapolis Microsystems WildStar reconfigurable hardware system. This system is populated with three Virtex-E field-programmable gate array (FPGA) parts and several memory ports. The issues of how the modified algorithm is divided between individual FPGA parts and how data flows through the memories are also discussed in this study. It presents and evaluates the final results and speedups against a comparable microprocessor solution from the time the Annapolis Microsystems WildStar was released." @default.
- W2479930167 created "2016-08-23" @default.
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- W2479930167 date "2008-01-01" @default.
- W2479930167 modified "2023-09-24" @default.
- W2479930167 title "SPIHT Image Compression" @default.
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- W2479930167 doi "https://doi.org/10.1016/b978-012370522-8.50036-4" @default.
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