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- W2480167722 abstract "This chapter describes the effects of jitter on SNR, assuming that the jitter is solely a combination of the internal ADC aperture jitter and the external sampling clock jitter. However, improper layout, grounding, and decoupling techniques can create additional clock jitter, which can drastically degrade dynamic performance, regardless of the specifications of the ADC or sampling clock oscillator. Oscillators are most often specified in terms of phase noise. The chapter shows how to approximate the rms jitter based upon the phase noise. The PLL approach with a standard VCO is an excellent one for generating sampling clocks where the rms jitter requirement is approximately 1 ps or greater. However, subpicosecond jitter requires either a VCXO-based PLL or a dedicated low noise crystal oscillator. DDSs, mixers, frequency dividers, and frequency doublers can be utilized in conjunction with PLLs to form what is generally referred to as a “hybrid” frequency synthesizer. The phase noise of a PLL can be controlled by the loop filter, the VCXO, and an output filter. DDS systems have phase noise, which is produced primarily by the finite resolution of the internal DAC. Semiconductor MC 100EL 16 or the NBSG 16 is an excellent choice for performing single-ended-to-differential clock conversion. These parts are basically ECL (Emitter–Coupled–Logic) designs, which can be operated on a single positive supply." @default.
- W2480167722 created "2016-08-23" @default.
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- W2480167722 date "2005-01-01" @default.
- W2480167722 modified "2023-10-14" @default.
- W2480167722 title "Sampling Clock Generation" @default.
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- W2480167722 doi "https://doi.org/10.1016/b978-075067841-4/50027-0" @default.
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