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• W2482613298 abstract "With the rapid increase in the size and scale of modern systems, topology-aware process mapping has become an important approach for improving system efficiency. A poor placement of processes across compute nodes could cause significant congestion within the interconnect. In this paper, we propose a new greedy mapping heuristic as well as a mapping refinement algorithm. The heuristic attempts to minimize a hybrid metric that we use for evaluating various mappings, whereas the refinement algorithm attempts to reduce maximum congestion directly. Moreover, we take advantage of parallelism in the design and implementation of our proposed algorithms to achieve scalability. We also use the underlying routing information in addition to the topology of the system to derive a better evaluation of congestion. Our experimental results with 4096 processes show that the proposed approach can provide more than 60% improvement in various mapping metrics compared to an initial in-order mapping of processes. Communication time is also improved by 50%. In addition, we also compare our proposed algorithms with 4 other heuristics from the LibTopoMap library, and show that we can achieve better mappings at a significantly lower cost." @default.
• W2482613298 created "2016-08-23" @default.
• W2482613298 creator A5007659072 @default.
• W2482613298 creator A5039854005 @default.
• W2482613298 date "2016-05-01" @default.
• W2482613298 modified "2023-09-26" @default.
• W2482613298 title "PTRAM: A Parallel Topology-and Routing-Aware Mapping Framework for Large-Scale HPC Systems" @default.
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• W2482613298 doi "https://doi.org/10.1109/ipdpsw.2016.146" @default.
• W2482613298 hasPublicationYear "2016" @default.
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