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- W2484968740 abstract "An asynchronous 2D-Torus Network-on-Chip (ATNoC) design based on System Verilog is implemented in this paper. A dynamic asynchronous XY routing algorithm DA-XY is proposed and designed as an Intellectual Property (IP) core and embedded to the ATNoC. Asynchronous circuit design methodology is used to design each routing node which could be divided into the following components, that is, receiving module, Hamming decoding module, routing analysis module, splitting module, arbiter module, Hamming encoding module and sending module. A test platform is built to analyze the function and the performance of the asynchronous NoC. The test result shows that the asynchronous NoC could support self-adaptive routing, multi-directional communication, and parallel multi-channel communications." @default.
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- W2484968740 date "2016-01-01" @default.
- W2484968740 modified "2023-10-06" @default.
- W2484968740 title "An Asynchronous 2D-Torus Network-on-Chip Using Adaptive Routing Algorithm" @default.
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- W2484968740 doi "https://doi.org/10.1007/978-3-319-42553-5_29" @default.
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