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- W2485759767 abstract "As R.E. Gomory of IBM has so aptly noted, “Far from being passive containers for microelectronic devices, the packages in today's advanced computers pose at least as many engineering challenges as the chips that they interconnect, power, and cool.” This is not an idle exaggeration, because packaging technology encompasses an integrated bundle of interdisciplinary concerns. It requires the expertise of scientists as well as mechanical, electrical, chemical, and materials engineers engaged in processing and assembling a host of different materials for a variety of functions. At least three levels of packaging architecture are required to interconnect, power, distribute signals, and cool chips in electronic equipment. Chip-level interconnections may be thought of as zero-level packaging. Individual dies encased in a single package then constitute the first level." @default.
- W2485759767 created "2016-08-23" @default.
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- W2485759767 date "2015-01-01" @default.
- W2485759767 modified "2023-10-11" @default.
- W2485759767 title "Packaging Materials, Processes, and Stresses" @default.
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- W2485759767 doi "https://doi.org/10.1016/b978-0-12-088574-9.00008-2" @default.
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